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ISL6412
Data Sheet March 20, 2007 FN9067.1
Triple Output, Low-Noise LDO Regulator with Integrated Reset Circuit
The ISL6412 is an ultra low noise triple output LDO regulator with microprocessor reset circuit and is optimized for powering wireless chip sets. The IC accepts an input voltage range of 3.0V to 3.6V and provides three regulated output voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-clean 2.8V (LDO3). On chip logic provides sequencing between LDO1 and LDO2 for the BBP/MAC and the I/O supply voltage outputs. LDO3 features ultra low noise that does not typically exceed 30V RMS to aid VCO stability. High integration and the thin Quad Flat No-lead (QFN) package makes the ISL6412 an ideal choice to power many of today's small form factor industry standard wireless cards such as PCMCIA, mini-PCI and Cardbus-32. The ISL6412 uses an internal PMOS transistor as the pass device. The ISL6412 also integrates a reset function, which eliminates the need for the additional reset IC required in WLAN applications. The IC asserts a RESET signal whenever the VIN supply voltage drops below a preset threshold, keeping it asserted for a time set by a capacitor to GND after VIN has risen above the reset threshold. FAULT1 indicates the loss of regulation on LDO1.
Features
* Small DC/DC Converter Size - Three LDOs and Reset Circuitry in a Low-Profile 4x4mm QFN Package * High Output Current - LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA - LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA - LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA * Ultra-Low Dropout Voltage - LDO2, 2.8V. . . . . . . . . . . . . . . . 125mV (typ.) at 225mA - LDO3, 2.8V. . . . . . . . . . . . . . . . 100mV (typ.) at 125mA * Ultra-Low Output Voltage Noise - <30VRMS (typ.) for LDO3 (VCO Supply) * Stable with Small Ceramic Output Capacitors * Extensive Protection and Monitoring Features - Over current protection - Short circuit protection - Thermal shutdown - FAULT indicator * Logic-Controlled Shutdown Pin * Integrated Microprocessor Reset Circuit - Programmable Reset Delay
Ordering Information
PART NUMBER ISL6412IR ISL6412IR-TK PART MARKING ISL6412IR ISL6412IR TEMP. RANGE (C) PACKAGE PKG. DWG. #
* Proven Reference Design for a Total WLAN System Solution * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Product Outline - Near Chip-Scale Package Footprint Improves PCB Efficiency and Is Thinner in Profile * Pb-Free Plus Anneal Available (RoHS Compliant)
-40 to +85 16 Ld 4x4 QFN L16.4x4 -40 to +85 16 Ld 4x4 QFN L16.4x4 -40 to +85 16 Ld 4x4 QFN L16.4x4 -40 to +85 16 Ld 4x4 QFN L16.4x4 (Pb-free) -40 to +85 16 Ld 4x4 QFN L16.4x4 (Pb-free)
ISL6412IR-T5K ISL6412IR ISL6412IRZ (Note 2) 6412IRZ
ISL6412IRZ-TK 6412IRZ (Notes 1, 2) NOTES:
Applications
* PRISM(R) 3 Chipsets - ISL37106P * WLAN Cards - PCMCIA, Cardbus32, MiniPCI Cards - Compact Flash Cards * Liberty Chipset * Hand-Held Instruments
1. Tape and Reel available. Add "-T" suffix for Tape and Reel Packing Option 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004, 2007. All Rights Reserved. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL6412 Pinout
ISL6412 (16 LD QFN) TOP VIEW
FAULT1
VIN 14
16 RESET CT SHDN NC 1 2 3 4 5 OUT3
15
13 12 11 10 9 OUT1 CC1 OUT2 CC2
6 CC3
7 GND3
Typical Application Schematic
+3.3V VIN + C4 3.3F 14 VIN 13 VIN 16 15
GND
VIN 8
NC
FAULT1
+1.8V VOUT1
NC
C8 0.01F
1 2 3 4
RESET CT SHDN NC
ISL6412
12 OUT1 11 CC1 10 OUT2 9 CC2 C5 0.033F C6 0.033F C2 3.3F C1 3.3F
+2.8V VOUT2
+2.8V VOUT3 C3 3.3F
Typical Bill Of Materials
REFERENCE DESIGNATOR C1, C2, C3, C4 C5, C6, C7 C8 U1 VALUE 3.3F, X7R 0.033F, X7R 0.01F, X7R ISL6412IR PACKAGE 1206 0603 0603 QFN16 MANUFACTURER TDK TDK/ANY TDK/ANY Intersil MANUFACTURER'S PART NUMBER C3216X7R1A106M C1608X7R1A333K C1608X7R1A103K ISL6412IR
2
5 6 7 8 C7 0.033F
OUT3 CC3 GND3 GND
FN9067.1 March 20, 2007
ISL6412 Functional Block Diagram
VIN BAND GAP REF. 1.2V VREF + WINDOW COMP LDO1 VIN
13
14
OUT1
12
15
FAULT1
EN THERMAL SHUTDOWN 150C
EN
CC1 LDO2 VIN
11
CONTROL LOGIC EN EN
OUT2 VREF EN CC2 CC2 OUT2
10
9
3
SHDN LDO3 VIN
2
CT RESET EN VREF EN CC3
OUT3 OUT3
5
1
RESET
CC3 8
6
GND
GND3
7
3
FN9067.1 March 20, 2007
ISL6412
Absolute Maximum Ratings
VIN, SHDN to GND/GND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V SET, CC, FAULT to GND/GND3 . . . . . . . . . . . . . . . . . -0.3V to 7.0V Output Current (Continuous) LDO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA LDO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA LDO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) QFN Package (Notes 3, 4) . . . . . . . . 46 9 Maximum Junction Temperature (Plastic Package) -55C to +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER GENERAL SPECIFICATIONS VIN Voltage Range Operating Supply Current Shutdown Supply Current SHDN Input Threshold
VIN = +3.3V, Compensation Capacitor = 33nF, TA = +25C, unless otherwise noted. TEST CONDITIONS MIN TYP MAX UNITS
3.0 IOUT = 0mA SHDN = GND VIH, VIN = 3V to 3.6V VIL, VIN = 3V to 3.6V 2.0 145 COUT = 10F, VOUT = 90% of final value Rising 75mV Hysteresis 2.4
3.3 830 5 150 20 120 2.45
3.6 1125 10 0.4 160 2.6
V A A V V C C s V
Thermal Shutdown Temperature (Note 7) Thermal Shutdown Hysteresis (Note 7) Start-up Time (Note 7) Input Undervoltage Lockout LDO1 SPECIFICATIONS Output Voltage (VOUT1) Output Voltage Initial Accuracy Line Regulation Load Regulation Maximum Output Current (IOUT1) (Note 7) Output Current Limit (Note 7) Output Voltage Noise (Note 7) LDO2 SPECIFICATIONS Output Voltage (VOUT2) Output Voltage Accuracy Maximum Output Current (IOUT2) (Note 7) Output Current Limit (Note 7) Dropout Voltage (Notes 5, 7) Line Regulation Load Regulation IOUT = 225mA VIN = 3.0V to 3.6V, IOUT = 10mA IOUT = 10mA to 225mA IOUT = 10mA, TA = -40C to 85C VIN = 3.6V 10Hz < f < 100kHz, COUT = 4.7F, IOUT = 50mA IOUT = 10mA, TA = -40C to 85C VIN = 3.0V to 3.6V, IOUT = 10mA IOUT = 10mA to 330mA
-2.0 -0.15 -1.5 330 500 -
1.8 0.0 600 115
2.0 0.15 1.5 1105 -
V % %/V % mA mA VRMS
-2.0 225 330 -0.15 -
2.8 125 0.0 0.2
2.0 900 160 0.15 1.0
V % mA mA mV %/V %
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ISL6412
Electrical Specifications
PARAMETER Output Voltage Noise (Note 7) VIN = +3.3V, Compensation Capacitor = 33nF, TA = +25C, unless otherwise noted. (Continued) TEST CONDITIONS 10Hz < f < 100kHz, IOUT = 10mA COUT = 2.2F COUT = 10F LDO3 SPECIFICATIONS Output Voltage (VOUT3) Output Voltage Accuracy Maximum Output Current (IOUT3) (Note 7) Output Current Limit (Note 7) Dropout Voltage (Notes 5, 7) Line Regulation Load Regulation Output Voltage Noise (Note 7) IOUT = 125mA VIN = 3.0V to 3.6V, IOUT = 10mA IOUT = 10mA to 125mA 10Hz < f < 100kHz, IOUT = 10mA COUT = 2.2F COUT = 10F RESET BLOCK SPECIFICATIONS Reset Threshold Reset Threshold Hysteresis (Note 7) VIN to Reset Delay RESET Active Timeout Period (Notes 6, 7) FAULT1 Rising Threshold Falling Threshold NOTES: 5. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V. 6. The RESET time is linear with CT at a slope of ~5ms/nF. Thus, at 10nF (0.01F) the RESET time is 50ms. 7. Guaranteed by design, not production tested. % of VOUT % of VOUT +5.5 -10.5 +8.0 -8.0 +10.5 -5.5 % % VCC = VTH to VTH - 100mV CT = 0.01F 2.564 6.3 50 2.630 20 2.66 V mV s ms 30 20 VRMS VRMS IOUT = 10mA, TA = -40C to +85C VIN = 3.6V -2.0 225 300 -0.15 2.8 450 100 0.0 0.2 2.0 840 160 0.15 1.0 V % mA mA mV %/V % 65 60 VRMS VRMS MIN TYP MAX UNITS
Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = +25C, Unless Otherwise Noted
SHDN 1V/DIV VOUT2 1V/DIV
SHDN 1V/DIV VOUT3 1V/DIV
VOUT2 1V/DIV VOUT3 1V/DIV
VOUT1 1V/DIV
VOUT1 1V/DIV 100s/DIV 100s/DIV
FIGURE 1. START-UP SEQUENCE
FIGURE 2. SHUTDOWN SEQUENCE
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FN9067.1 March 20, 2007
ISL6412 Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = +25C, Unless Otherwise Noted (Continued)
SHDN 2V/DIV
VOUT1 50mV/DIV
VOUT1 2V/DIV
RESET 2V/DIV IOUT1 200mA/DIV FAULT 2V/DIV 20ms/DIV 1ms/DIV
FIGURE 3. SHUTDOWN, FAULT, and RESET OPERATION
FIGURE 4. LDO1 TRANSIENT RESPONSE (10mA to 330mA)
VOUT2 100mV/DIV
VOUT3 100mV/DIV
IOUT2 100mA/DIV 1ms/DIV
IOUT3 50mA/DIV 1ms/DIV
FIGURE 5. LDO2 TRANSIENT RESPONSE (10mA to 200mA)
FIGURE 6. LDO3 TRANSIENT RESPONSE (10mA to 100mA)
VIN 0.5V/DIV VIN 0.5V/DIV RESET 0.5V/DIV RESET 0.5V/DIV CT 0.5V/DIV CT 0.5V/DIV
20ms/DIV
100ms/DIV
FIGURE 7. RESET DELAY DURING START-UP (CT = 0.01F)
FIGURE 8. RESET DELAY DURING START-UP (CT = 0.1F)
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FN9067.1 March 20, 2007
ISL6412 Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = +25C, Unless Otherwise Noted (Continued)
-10
-20 PSRR (dB)
-30
FAULT 1V/DIV
-40
-50
-60 VOUT1/2/3 1V/DIV 500ms/DIV 10 100 1k 10k 100k 1M FREQUENCY (A)
FIGURE 9. THERMAL SHUTDOWN OPERATION
FIGURE 10. LDO1 POWER SUPPLY REJECTION (IOUT1 = 100mA, COUT = 10F MLCC)
VIN 0.5V/DIV
VIN = 2.7V
VOUT1 0.5V/DIV
FAULT 0.5V/DIV
FIGURE 11. VOUT1 REGULATION DOWN TO VIN = 2.7V; FAULT MONITORS VOUT1 ONLY
Pin Descriptions
OUT1 - This pin is the output for LDO1. Bypass with a minimum of 2.2F, low ESR capacitor to GND for stable operation. VIN - Supply input pins. Connect to input power source. Bypass with a minimum 2.2F capacitor to GND. Both VIN pins must be tied together on the PC board, close to the IC. GND - Ground for LDO1 and LDO2. CC1 - Compensation Capacitor for LDO1. Connect a 0.033F capacitor from CC1 to GND. SHDN - Shutdown input for all LDOs. Connect to VIN for normal operation. Drive this pin LOW to turn off all LDOs.
OUT2 - This pin is the output for LDO2. Bypass with a minimum of 2.2F, low ESR capacitor to GND for stable operation. CT - Timing pin for the RESET circuit pulse width. CC2 - Compensation capacitor for LDO2. Connect a 0.033F capacitor from CC2 to GND. OUT3 - This pin is output for LDO3. Bypass with a minimum of 2.2F, low ESR capacitor to GND3 for stable operation. GND3 - Ground pin for LDO3. CC3 - Compensation capacitor for LDO3. Connect a 0.033F capacitor from CC3 to GND3. FAULT1 - This is the power good indicator for LDO1. When the 1.8V output is out of regulation this pin goes LOW. This
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FN9067.1 March 20, 2007
ISL6412
pin also goes LOW during thermal shutdown or an overcurrent event on LDO1. Connect this pin to GND, if unused. RESET - This pin is the active-LOW output of the push-pull output stage of the integrated reset supervisory circuit. The reset circuit monitors VIN and asserts a RESET output at this pin, if VIN falls below the RESET threshold. The RESET output remains LOW, while the VIN pin voltage is below the reset threshold, and for at least 25ms, after VIN rises above the RESET threshold. The voltage at the CT pin is compared to the 1.2V bandgap voltage. The charging of the CT capacitor behaves like an RC network and the RESET delay can be approximated by: Td = -R*C*ln(1-1.2V/VIN) Where C is the capacitor at CT, and R is 11.1M for VIN = 3.3V. With no capacitor on the CT pin the RESET delay will be close to zero. Figure 12 shows the RESET delay vs CT capacitance.
500 400 DELAY (ms) 300 200 100 0 0 0.01 0.02 0.03 0.04 CT (F) 0.05 0.06 0.07 0
Functional Description
The ISL6412 is a 3-in-1 multi-output, low dropout, regulator designed for wireless chipset power applications. It supplies three fixed output voltages 1.8V, 2.8V and 2.8V. Each LDO consists of a 1.2V reference, error amplifier, MOSFET driver, P-Channel pass transistor, dual-mode comparator and internal feedback voltage divider. The 1.2V band gap reference is connected to the error amplifier's inverting input. The error amplifier compares this reference to the selected feedback voltage and amplifies the difference. The MOSFET driver reads the error signal and applies the appropriate drive to the P-Channel pass transistor. If the feedback voltage is lower then the reference voltage, the pass transistor gate is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher then the reference voltage, the pass transistor gate is driven higher, allowing less current to pass to the output. The output voltage is fed back through an internal resistor divider connected to OUT1/OUT2/OUT3 pins. Additional blocks include an output overcurrent protection, thermal sensor, fault detector, RESET function and shutdown logic.
FIGURE 12. RESET DELAY vs CT CAPACITANCE
Output Voltages
The ISL6412 provides fixed output voltages for use in Wireless Chipset applications. Internal trimmed resistor networks set the typical output voltages as shown here: VOUT1 = 1.8V; VOUT2 = 2.8V; VOUT3 = 2.8V.
Shutdown
Pulling the SHDN pin LOW puts the complete chip into shutdown mode, and supply current drops to 5A typical. This input has an internal pull-up resistor, so that in normal operation the outputs are always enabled; external pull-up resistors are not required.
Internal P-Channel Pass Transistors
The ISL6412 features a typical 0.5 rDS(ON) P-channel MOSFET pass transistors. This provides several advantages over similar designs using PNP bipolar pass transistors. The P-Channel MOSFET requires no base drive, which reduces quiescent current considerably. PNP based regulators waste considerable current in dropout when the pass transistor saturates. They also use high base drive currents under large loads. The ISL6412 does not suffer from these problems.
Current Limit
The ISL6412 monitors and controls the pass transistor's gate voltage to limit the output current. The current limit for LDO1 is 500mA, LDO2 is 330mA and LDO3 is 300mA. The output can be shorted to ground without damaging the part due to the current limit and thermal protection features.
Integrated Reset for MAC/Baseband Processors
The ISL6412 includes a microprocessor supervisory block. This block eliminates the extra reset IC and external components needed in wireless chipset applications. This block performs a single function; it asserts a RESET signal whenever the VIN supply voltage decreases below a preset threshold, keeping it asserted for a programmable time (set by external capacitor CT) after the VIN pin voltage has risen above the reset threshold. The reset threshold for the ISL6412 is 2.63V typical. 8
FN9067.1 March 20, 2007
ISL6412
Thermal Overload Protection
Thermal overload protection limits total power dissipation in the ISL6412. When the junction temperature (TJ) exceeds +150C, the thermal sensor sends a signal to the shutdown logic, turning off the pass transistor and allowing the IC to cool. The pass transistor turns on again after the IC's junction temperature typically cools by 20C, resulting in a pulsed output during continuous thermal overload conditions. Thermal overload protection protects the ISL6412 against fault conditions. For continuous operation, do not exceed the absolute maximum junction temperature rating of +150C.
FAULT Functionality
TABLE 1. EVENT Below UVLO threshold VOUT1 = 1.8V 8% typ VOUT2/VOUT3 not in regulation VOUT1 not in regulation VOUT2 and VOUT3 are in regulation Thermal Shutdown Normal Shutdown with SHDN pin Overcurrent only on LDO1 Overcurrent only on LDO2/LDO3 FAULT1 L H L L L L H
Operating Region and Power Dissipation
The maximum power dissipation of ISL6412 depends on the thermal resistance of the IC package and circuit board, the temperature difference between the die junction and ambient air, and the rate of air flow. The power dissipated in the device is: PT = P1 + P2 + P3, where P1 = IOUT1 (VIN - VOUT1) P2 = IOUT2 (VIN - VOUT2) P3 = IOUT3 (VIN- VOUT3) The maximum power dissipation is: Pmax = (Tjmax - TA)/JA Where Tjmax = +150C, TA = ambient temperature, and JA is the thermal resistance from the junction to the surrounding environment. The ISL6412 package features an exposed thermal pad on its underside. This pad lowers the thermal resistance of the package by providing a direct heat conduction path from the die to the PC board. Additionally, the ISL6412's ground (GND/GND3) performs the dual function of providing an electrical connection to system ground and channeling heat away. Connect the exposed backside pad and GND to the system ground using a large pad or ground plane, or through multiple vias to the ground plane layer.
Applications Information
Capacitor Selection and Regulator Stability
Capacitors are required at the ISL6412's input and output for stable operation over the entire load range and the full temperature range. Use >1F capacitor at the input of ISL6412. The input capacitor lowers the source impedance of the input supply. Larger capacitor values and lower ESR provides better PSRR and line transient response. The input capacitor must be located at a distance of not more then 0.5 inches from the VIN pins of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used as an input capacitor. The output capacitor must meet the requirements of minimum amount of capacitance and ESR for all three LDO's. The ISL6412 is specifically designed to work with small ceramic output capacitors. The output capacitor's ESR affects stability and output noise. Use an output capacitor with an ESR of 50m or less to insure stability and optimum transient response. For stable operation, a ceramic capacitor, with a minimum value of 3.3F, is recommended for VOUT1 for 300mA output current, and 2.2F is recommended for VOUT2 and VOUT3 each at 200mA load current. There is no upper limit to the output capacitor value. Larger capacitor can reduce noise and improve load transient response, stability and PSRR. Higher value of output capacitor (10F) is recommended for LDO3 when used to power VCO circuitry in wireless chipsets. The output capacitor should be located very close to VOUT pins to minimize impact of PC board inductances and the other end of the capacitor should be returned to a clean analog ground.
Integrator Circuitry
The ISL6412 uses an external 33nF compensation capacitor for minimizing load and line regulation errors and for lowering output noise. When the output voltage shifts due to varying load current or input voltage, the integrator capacitor voltage is raised or lowered to compensate for the systematic offset at the error amplifier. Compensation is limited to 5% to minimize transient overshoot when the device goes out of dropout, current limit, or thermal shutdown.
Input-Output (Dropout) Voltage
A regulator's minimum input-output voltage differential (or dropout voltage) determines the lowest usable supply voltage. Because the ISL6412 uses a P-channel MOSFET pass transistor, its dropout voltage is a function of rDS(ON) (typically 0.5) multiplied by the load current.
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FN9067.1 March 20, 2007
ISL6412 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.50 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN9067.1 March 20, 2007

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